Programmable integrated circuits (e.g., programmable logic devices, field programmable gate arrays (FPGAs), etc.) and non-programmable integrated circuits can include arithmetic units (e.g., multipliers, adders, digital signal processors, accumulators, and the like) which are designed to receive multiple input operands and generate a resulting value—e.g., performing an add, subtract, multiple, or multiply accumulator (MAC) operation. The arithmetic units generate an output with a fixed number of bits (e.g., a 48 bit output) which defines the precision of the unit. However, rather than performing a single operation, the arithmetic units can be used to perform multiple reduced precision arithmetic operations in parallel. For example, rather than performing a single operation using 16 bit operands, the unit can perform two operations using 8 bit operands. However, the results of the two 8-bit operations are still stored within the same 48 bit output vector of the arithmetic unit. For example, a first sub-portion of the output vector is allotted to the first 8-bit operation while a second sub-portion of the output vector is allotted to the second 8-bit operation. However, in a chain of arithmetic units where the results of one arithmetic unit is used as an input to the next unit in the chain, the results may begin to overflow. For example, the first sub-portion of the output vectors may not be sufficient to store the results of the operation, in which case, the most significant bits of the first operation may interfere with the least significant bits of the second operation in the output vector.
To prevent this overflow, guard bits can be allocated in the output vector which provides a buffer between the portions of the vector assigned to the two operations. When in the chain the results of the first operation would overflow, this is absorbed by the guard bits. As a result, the guard bits provide a limited buffer which permits the first operation to grow without affecting the bits in the output vector assigned to the second operation.